## EC2203 - Digital Electronics (DE) Part B - Important Questions | EC 2203 PArt B (16 MArks) Expected Questions for ECE - Third (3rd) Semester - www.iannauniversity.com ...

## EC2203 - Digital Electronics (DE) Part B - Important Questions | EC 2203 PArt B (16 MArks) Expected Questions for ECE - Third (3rd) Semester - www.iannauniversity.com ...

**Posted by R.Anirudhan**

**WWW.IANNAUNIVERSITY.COM**

**Unit -1**

1.(a) (i) Express the Boolean function F = XY + XZ in product of Maxterm.(6)

(ii) Reduce the following function using K-map technique

f ( A, B, C , D ) = π (0, 3, 4, 7, 8, 10, 12, 14 ) + d (2, 6) . (10) - EXPECTED this type of Problems

2. Simplify the following Boolean function by using Quine-Mcclusky method F ( A, B, C , D ) = ∑ (0, 2, 3, 6, 7, 8, 10, 12, 13) . (16) - EXPECTED this type of Problems.

(ii) Reduce the following function using K-map technique

f ( A, B, C , D ) = π (0, 3, 4, 7, 8, 10, 12, 14 ) + d (2, 6) . (10) - EXPECTED this type of Problems

2. Simplify the following Boolean function by using Quine-Mcclusky method F ( A, B, C , D ) = ∑ (0, 2, 3, 6, 7, 8, 10, 12, 13) . (16) - EXPECTED this type of Problems.

3. (a) Find a Min SOP and Min POS for f = b’c’d + bcd + acd’ + a’b’c + a’bc’d - EXPECTED this type of Problems.

4. (a) Simplify the following using the Quine – McClusky minimization technique

D = f(a,b,c,d) = _ (0,1,2,3,6,7,8,9,14,15).Does Quine –McClusky take care of don’t

care conditions? In the above problem, will you consider any don’t care conditions? Justify your answer

(b) List also the prime implicants and essential prime implicants for the above case

5.(a) Determine the MSP and MPS focus of F= _ (0, 2, 6, 8, 10, 12, 14, 15)

(b) State and Prove Demorgan’s theorem

**Unit -2**.

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1.Explain in detail the look ahead carry generator - Expected

2. (i)Implement full subtractor using demultiplexer. (10)

(ii) Implement the given Boolean function using 8 : 1 multiplexer F ( A, B, C ) = ∑ (1, 3, 5, 6) . (6) - Expected

3. Design a excess 3 to BCD code convertor

4. (a) Design a full sub tractor

(b) How to it differ from a full sub tractor

F2 = a’ + b’c + bc’ - Expected

6. Realize a BCD to Excess 3 code conversion circuit starting from its truth table.

**Unit -3**

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1. (i) How will you convert a D flipflop into JK flipflop? (8)

(ii) Explain the operation of a JK master slave flipflop. (8) - Expected

2. Explain in detail the operation of a 4 bit binary ripple counter. (16) - Expcted

3. Explain in detail the operation of 4 bit ripple counter (10) - Expected

4. Draw the state diagram and characteristics equation of T FF, D FF and JK FF - Expected (any one)

1.(a) Implement the following Boolean functions with a PLA

F1 ( A, B, C ) = ∑ (0, 1, 2, 4 )

F2 ( A, B, C ) = ∑ (0, 5, 6, 7)

F3 ( A, B, C ) = ∑ (0, 3, 5, 7) . (16) - Expected

2. Design a combinational circuit using a ROM. The circuit accepts a three bit number and outputs a binary number equal to the square of the input number. (16) - Expected

3.(a) Discuss a decade counter and its working principle

(b) Draw as asynchronous 4 bit up-down counter and explain its working

4. (a) How is the design of combinational and sequential logic circuits possible with PLA?

(b) Mention the two models in a sequential circuit and distinguish between them - Expected

5 Design a modulo 5 synchronous counter using JK FF and implement it. Construct its

timing diagram - Expected

1.(a) Design a three bit binary counter using T flipflops. (16) - Expected

2. Design a negative-edge triggered ‘T flipflop’. (16) - Expected

3. Write a verilog coding for full adder (8)

4.What is the objective of state assignment in asynchronous circuit? Give hazard – free

realization for the following Boolean function f(A,B,C,D) = _M(0,2,6,7,8,10,12) - Expected

5. Summarize the design procedure for asynchronous sequential circuit

a. Discuss on Hazards and races

b. What do you know on hardware descriptive languages?

**ALL THE BEST!!!**

**By**

**R.Anirudhan**

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