## CS2202 DIGIAL PRINCIPLES AND SYSTEMS DESIGN ANNA UNIVERSITY QUESTION PAPER APRIL/MAY 2010 for CSE (3rd sem) ...

Posted by R.Anirudhan

B.E./B.Tech. DEGREE EXAMINATION, APRIL/MAY 2010.
Third Semester
Computer Science and Engineering
CS2202 — DIGIAL PRINCIPLES AND SYSTEMS DESIGN
(Common to Information Technology)
(Regulation 2008)
Time: Three hours Maximum: 100 Marks
PART A — (10 × 2 = 20 Marks)
1. Convert the 10 ) 513 . 153 ( to Octal.
2. Simplify the following Boolean functions to a minimum number of literals
(a) ) )( ( y x y x ′ + +
(b) yz z x xy + ′ + .
3. Distinguish between the combinational and sequential logic circuits.
4. What do you mean by HDL?
5. What is Multiplexer?
6. Define Encoder.
7. Differentiate Flip-Flop from Latches.
8. Draw the excitation table and state diagram for JK and SR Flip-Flop.
9. What is Race Conditions?
10. What happens when a Hazard happens in a logic circuit?

PART B — (5 × 16 = 80 Marks)
11. (a) (i) Simplify the following Boolean function F together with don’t-care
condition d, and then express the simplified function in sum of
minterms
) 5 , 2 , 0 ( ) 15 , 11 , 7 , 3 , 1 ( ) , , , ( d z y x w F ∑ + ∑ = (10)
(ii) Implement the following Boolean function with NAND gates.
) 7 , 5 , 4 , 3 , 2 , 1 ( ) , , ( = z y x F (6)
Or
(b) Determine the prime-implicants of the Boolean function by using the
tabulation method.
) 15 , 11 , 10 , 9 , 8 , 7 , 6 , 4 , 1 ( ) , , , ( ∑ = z y x w F (16)
12. (a) Design a combinational logic diagram for BCD to Excess-3 code
converter. (16)
Or
(b) (i) Design a Full Adder circuit with necessary diagram. (10)
(ii) Write the HDL description of the circuit specified by the following
Boolean function. (6)
C y
C AB x
′ =
+ =
13. (a) (i) Design a 3 to 8-line decoder with necessary diagram. (8)
(ii) Implement the given Boolean function using 4 × 1 multiplexer.
( ) 7 , 6 , 2 , 1 ) , , ( Î£ = z y x F (8)
Or
(b) We have found a minimum sum of products expression for each of two
function, F and G, minimizing them individually (no sharing)
Z Y X Y W F ′ + ′ =
Z Y W Y X Y X W G ′ ′ + ′ + ′ ′ = .
(i) Implement them with a ROM. (8)
(ii) Implement them in the PLA using no more than four terms. (8)
14. (a) Design a synchronous sequential circuit using JK flip-flop to generate the
following sequence and repeat. (16)
0, 1, 2, 4, 5, 6
Or
(b) What is the aim of state reduction? Reduce the given state diagram and
prove that the both state diagrams are equal. (16)
15. (a) With suitable example and diagram explain the hazards in combinational
and sequential logic circuits. (16)
Or
(b) With necessary example and diagram explain the concept of reduction of
state and flow tables. (16)

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