EI2405 VLSI LABORATORY Syllabus - EIE 7th Semester - Anna University


EI2405                                               VLSI LABORATORY                                                L T P C
0 0  3 2

OBJECTIVE
To study synthesis, simulation and schematic of various digital combinational circuits using
FPGA on Xilink simulator.

1.  Study of Synthesis tools
·    Half and full adder.
·    Decoder 2 x 4, 3 x 8
·    Priority encoder.
·    Ripple adder.
·    4 Bit ripple counter.
·    Code conversion.
All the above synthesis in three modeling styles - data flow, structural and behavioral
2.  Study of Simulation using tools
·    Half adder.
·    Multiplexer – 2 x 1, 4 x 1
·    Demultiplexer 1 x 2, 1 x 4
All the above synthesis in three modeling styles - data flow, structural and behavioral

3.  Study of Simulation using tools
·    Flipflop D, T
·    Priority encoder.
·    Ripple adder.
·    4 Bit ripple counter.
All the above synthesis in three modeling styles - data flow, structural and behavioral

4.  Study of development tool for FPGAs for schematic entry and verilog
·    Full adder, half adder.
·    Demultiplexer 1 x 2, 1 x 4.

5.  Design and simulation of pipelined serial and parallel adder to add/ subtract 8 number of size,
12 bits each in 2's complement.

6.  Place and Root and Back annotation for FPGAs

7.  Design and simulation of back annotated verilog files for multiplying two signed, 8 bit numbers in
2's complement.

8.  Study of FPGA board and testing on board LEDs and switches using verilog code.

9.  Design a Realtime Clock (2 digits, 7 segments LED displays each for HRS., MTS, and SECS.)
and demonstrate its  working on the FPGA board.
·    to display binary number on the FPGA.

10. Design of traffic light controller using verilog tools .
·    Movement of vehicles in any direction or pedestrian in any direction.
DETAILED SYLLABUS
1.    STUDY OF SYNTHESIS TOOLS
Adder/encoder/decoder/counter/converter.

AIM
To study the synthesis of  various combinational circuits on Xilink(ISE9.1) tool usingHardware
Descriptive Language(HDL).

EXERCISE
Write a HDL program in three modeling styles - data flow, structural and behavioral. using verilog and perform the synthesis of following combinational circuits
·        Half and full adder.
·        Decoder 2 x 4, 3 x 8
·        Priority encoder.
·        Ripple adder.
·        4 Bit ripple counter.
·         Code conversion.
2.    STUDY OF SIMULATION USING TOOLS
Adder/encoder/decoder/counter/multiplexer.


AIM
To study the simulation of  various combinational circuits on Xilink(ISE9.1) tool using Hardware
Descriptive Language(HDL).


EXERCISE
Write a HDL program in three modeling styles - data flow, structural and behavioral. using verilog and simulate the following combinational circuits
·     Half adder.
·     Multiplexer – 2 x 1, 4 x 1
·     Demultiplexer 1 x 2, 1 x 4

3.    STUDY OF SIMULATION USING TOOLS

Adder/encoder/decoder/counter/multiplexer.


AIM
To study the simulation of  various combinational circuits on Xilink(ISE9.1) tool using Hardware
Descriptive Language(HDL).

EXERCISE
Write a HDL program in three modeling styles - data flow, structural and behavioral.using verilog and simulate the following combinational circuits
·      Flipflop D, T
·      Priority encoder.
·      Ripple adder.
·      4 Bit ripple counter
4. STUDY OF DEVELOPMENT TOOL FOR FPGAS FOR SCHEMATIC ENTRY AND VERILOG.

Adder /demultiplexer.

AIM

To draw the schematic and generate the verilog code.

EXERCISE

Draw the schematic using Xilink(ISE9.1) tool and generate the verilog code for the following digital circuits and observe the simulated output
a.  Full adder, half adder.

b.  Demultiplexer 1 x 2, 1 x 4.



5. DESIGN AND SIMULATION OF PIPELINED SERIAL  AND PARALLEL  ADDER TO ADD/ SUBTRACT 8 NUMBER OF SIZE, 12 BITS EACH IN 2'S COMPLEMENT.
AIM

To design and simulate the pipelined 12 bit serial/parallel adder/subtractor.

EXERCISE

1. Write a verilog code to add/subtract 8 numbers of 12 bits each and verify the result after addition of every 2 numbers
2. Verify the result after adding all 8 numbers and simulate the output.


6.  PLACE AND ROOT AND BACK ANNOTATION FOR FPGAS AIM

To calculate the propagation delay produced by back annotated circuit from the    already software designed circuit..
EXERCISE

Write the verilog code and develop the following combinational circuit using s/w in the design layout that is produced. Make the required changes in the rooting as per the required propagation delay.
1.                  Multiplexer/Demultiplexer

2.                  Encoder/Decoder.

7. DESIGN AND SIMULATION OF BACK ANNOTATED VERILOG FILES FOR MULTIPLYING TWO SIGNED, 8 BIT NUMBERS IN 2'S COMPLEMENT. DESIGN MUST BE PIPELINED AND COMPLETELY RTL COMPLIANT
AIM

To design and simulate back annotated circuit using verilog code.

EXERCISE

Write the verilog code and develop the following combinational circuit using s/w in      the design layout that is produced.
1. Pipelined structure of multiplication of two signed 8 bit numbers.

2. View RTL model

8. STUDY OF  FPGA BOARD   AND  TESTING  ON BOARD  LEDS  AND  SWITCHES  USING VERILOG CODE.

AIM
To  study  the  FPGA  board  and  testing  on-board  LED’s  and  switches  using  ISE9.1 simulator.
EXERCISE
·    Write the verilog code in three modeling styles - data flow, structural and behavioral to accept the input from switches and display the output in LEDs.
·    Synthesis the program and view RTL model.
·    Download the program into FPGA for testing on board LED’s and switches.

9.  Design a realtime clock (2 digits, 7 segments led displays each for hrs., mts, and secs.) and demonstrate its  working on the fpga board. an expansion card is required for the displays.
c.        to display binary number on the FPGA.
AIM
To design and test the real time clock on FPGA board.
EXERCISE
·    Write the verilog code to display hrs, mts and secs.
·    Synthesis, simulate and download the program on the RTC board.

10.       Design of traffic light controller using verilog tools .
d.  Movement of vehicles in any direction or pedestrian in any direction.

AIM

To design and test the traffic light controller using FPGA board.

EXERCISE
·    Write the verilog code to implement different sequences of traffic light.
·    Synthesis, simulate and download the program on the traffic light controller board.


REQUIREMENT FOR A BATCH OF 30 STUDENTS
S.No.
Name of the Equipments
Quantity
1.
Software Simulation, Synthesis, back annotation, place & route

Xlinx ISE (latest version)
5 User License (minimum)
2.
Spartan 2E boards
5 Nos.
3.
Spartan 3 AN boards
1 No.
4.
Add on boards

1.      Real  - time clock
2.      2.  Traffic light control
3.      3. LED displays with switches
4.      4.  I/O boards



1 No.
1 No.
1 No.
1 No.
5.
Multimeter
2 Nos.










By Vinoth
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