Digital Logic Families

Logic families can be classified broadly according to the technologies they are  
built with. The various technologies are listed below.
·         DL : Diode Logic.
·         RTL : Resistor Transistor Logic.
·         DTL : Diode Transistor Logic.
·         HTL : High threshold Logic.
·         TTL : Transistor Transistor Logic.
·         I2L : Integrated Injection Logic.
·         ECL : Emitter coupled logic.
·         MOS : Metal Oxide Semiconductor Logic (PMOS and NMOS).
·         CMOS : Complementary Metal Oxide Semiconductor Logic.
Among these, only CMOS is most widely used by the ASIC (Chip) designers.
Basic Concepts
    • Fan-in.
    • Fan-out.
    • Noise Margin.
    • Power Dissipation.
    • Gate Delay.
    • Wire Delay.
    • Skew.
    • Voltage threshold
Fan – in:
Fan-in is the number of inputs a gate has, like a two input AND gate has fan-in of two, a three input NAND gate as a fan-in of three. So a NOT gate always has a fan-in of one. The figure below shows the effect of fan-in on the delay offered by a gate for a CMOS based gate. Normally delay increases following a quadratic function of fan-in.
Fan – out:
The number of gates that each gate can drive, while providing voltage levels in     the guaranteed range, is called the standard load or fan-out. The fan-out really depends on the amount of electric current a gate can source or sink while driving other gates. The effects of loading a logic gate output with more than its rated fan-out has the following effects.
    • In the LOW state the output voltage VOL may increase above VOLmax.
    • In the HIGH state the output voltage VOH may decrease below VOHmin.
    • The operating temperature of the device may increase thereby reducing the reliability of the device and eventually causing the device failure.
    • Output rise and fall times may increase beyond specifications
    • The propagation delay may rise above the specified value.
Normally as in the case of fan-in, the delay offered by a gate increases with the increase in fan-out.
Gate Delay
Gate delay is the delay offered by a gate for the signal appearing at its input, before it reaches the gate output. The figure below shows a NOT gate with a delay of "Delta", where output X' changes only after a delay of "Delta". Gate delay is also known as propagation delay.
Gate delay is not the same for both transitions, i.e. gate delay will be different for low to high transition, compared to high to low transition.Low to high transition delay is called turn-on delay and High to low transition delay is called turn-off delay.
Wire Delay
Gates are connected together with wires and these wires do delay the signal they carry, these delays become very significant when frequency increases, say when the transistor sizes are sub-micron. Sometimes wire delay is also called flight time (i.e. signal flight time from point A to B). Wire delay is also known as transport delay.
The same signal arriving at different parts of the design with different phase is known as skew. Skew normally refers to clock signals. In the figure below, clock signal CLK reaches flip-flop FF0 at time t0, so with respect to the clock phase at the source, it has at FF0 input a clock skew of t0 time units. Normally this is expressed in nanoseconds.
The waveform below shows how clock looks at different parts of the design.
Logic levels
Logic levels are the voltage levels for logic high and logic low.

·         VOHmin : The minimum output voltage in HIGH state (logic '1'). VOHmin is 2.4 V for TTL and 4.9 V for CMOS.
·         VOLmax : The maximum output voltage in LOW state (logic '0'). VOLmax is 0.4 V for TTL and 0.1 V for CMOS.
·         VIHmin : The minimum input voltage guaranteed to be recognised as logic 1. VIHmin is 2 V for TTL and 3.5 V for CMOS.
·         VILmax : The maximum input voltage guaranteed to be recognised as logic 0. VILmax is 0.8 V for TTL and 1.5 V for CMOS.
Current levels
·         IOHmin: The maximum current the output can source in HIGH state while still maintaining the output voltage above VOHmin.
·         IOLmax : The maximum current the output can sink in LOW state while still maintaining the output voltage below VOLmax.
·         IImax : The maximum current that flows into an input in any state (1µA for CMOS).
Noise Margin
Gate circuits are constructed to sustain variations in input and output voltage levels. Variations are usually the result of several different factors.
·         Batteries lose their full potential, causing the supply voltage to drop
·         High operating temperatures may cause a drift in transistor voltage and current characteristics
·         Spurious pulses may be introduced on signal lines by normal surges of current in neighbouring supply lines.
All these undesirable voltage variations that are superimposed on normal operating voltage levels are called noise. All gates are designed to tolerate a certain amount of noise on their input and output ports. The maximum noise voltage level that is tolerated by a gate is called noise margin. It derives from I/P-O/P voltage characteristic, measured under different operating conditions. It's normally supplied from manufacturer in the gate documentation.
·         LNM (Low noise margin): The largest noise amplitude that is guaranteed not to change the output voltage level when superimposed on the input voltage of the logic gate (when this voltage is in the LOW interval). LNM=VILmax-VOLmax.
·         HNM (High noise margin): The largest noise amplitude that is guaranteed not to change the output voltage level if superimposed on the input voltage of the logic gate (when this voltage is in the HIGH interval). HNM=VOHmin-VIHmin
tr (Rise time)
The time required for the output voltage to increase from VILmax to VIHmin.
tf (Fall time)
The time required for the output voltage to decrease from VIHmin to VILmax.
tp (Propagation delay)
The time between the logic transition on an input and the corresponding logic transition on the output of the logic gate. The propagation delay is measured at midpoints.
Power Dissipation
Each gate is connected to a power supply VCC (VDD in the case of CMOS). It draws a certain amount of current during its operation. Since each gate can be in a High, Transition or Low state, there are three different currents drawn from power supply.
·         ICCH: Current drawn during HIGH state.
·         ICCT: Current drawn during HIGH to LOW, LOW to HIGH transition.
·         ICCL: Current drawn during LOW state.
For TTL, ICCT the transition current is negligible, in comparison to ICCH and ICCL. If we assume that ICCH and ICCL are equal then,
Average Power Dissipation = Vcc * (ICCH + ICCL)/2
For CMOS, ICCH and ICCL current is negligible, in comparison to ICCT. So the Average power dissipation is calculated as below.
Average Power Dissipation = Vcc * ICCT.
So for TTL like logics family, power dissipation does not depend on frequency of operation, and for CMOS the power dissipation depends on the operation frequency.
Power Dissipation is an important metric for two reasons. The amount of current and power available in a battery is nearly constant. Power dissipation of a circuit or system defines battery life: the greater the power dissipation, the shorter the battery life. Power dissipation is proportional to the heat generated by the chip or system; excessive heat dissipation may increase operating temperature and cause gate circuitry to drift out of its normal operating range; will cause gates to generate improper output values. Thus power dissipation of any gate implementation must be kept as low as possible.
Moreover, power dissipation can be classified into Static power dissipation and Dynamic power dissipation.
·         Ps (Static Power Dissipation): Power consumed when the output or input are not changing or rather when clock is turned off. Normally static power dissipation is caused by leakage current. (As we reduce the transistor size, i.e. below 90nm, leakage current could be as high as 40% of total power dissipation).
·         Pd (Dynamic Power Dissipation): Power consumed during output and input transitions. So we can say Pd is the actual power consumed i.e. the power consumed by transistors + leakage current.
Total power dissipation = static power dissipation + dynamic power dissipation.
Diode Logic
In DL (diode logic), all the logic is implemented using diodes and resistors. One basic thing about the diode is that diode needs to be forward biased to conduct. Below is the example of a few DL logic circuits.
When no input is connected or driven, output Z is low, due to resistor R1. When high is applied to X or Y, or both X and Y are driven high, the corresponding diode get forward biased and thus conducts. When any diode conducts, output Z goes high.
Resistor Transistor Logic
In RTL (resistor transistor logic), all the logic are implemented using resistors and transistors. One basic thing about the transistor (NPN), is that HIGH at input causes output to be LOW (i.e. like a inverter). Below is the example of a few RTL logic circuits.
A basic circuit of an RTL NOR gate consists of two transistors Q1 and Q2, connected as shown in the figure above. When either input X or Y is driven HIGH, the corresponding transistor goes to saturation and output Z is pulled to LOW.
Diode Transistor Logic
In DTL (Diode transistor logic), all the logic is implemented using diodes and transistors. A basic circuit in the DTL logic family is as shown in the figure below. Each input is associated with one diode. The diodes and the 4.7K resistor form an AND gate. If input X, Y or Z is low, the corresponding diode conducts current, through the 4.7K resistor. Thus there is no current through the diodes connected in series to transistor base. Hence the transistor does not conduct, thus remains in cut-off, and output out is high.
If all the inputs X, Y, Z are driven high, the diodes in series conduct, driving the transistor into saturation. Thus output out is Low.
Transistor Transistor Logic
In Transistor Transistor logic or just TTL, logic gates are built only around transistors. TTL was developed in 1965. Through the years basic TTL has been improved to meet performance requirements. There are many versions or families of TTL.
·         Standard TTL.
·         High Speed TTL
·         Low Power TTL
·         Schhottky TTL
TTL families have three configurations for outputs.
·         Totem - Pole output.
·         Open Collector Output.
·         Tristate Output.
The input stage, which is used with almost all versions of TTL, consists of an input transistor and a phase splitter transistor. Input stage consists of a multi emitter transistor as shown in the figure below. When any input is driven low, the emitter base junction is forward biased and input transistor conducts. This in turn drives the phase splitter transistor into cut-off.         

Totem - Pole Output
Below is the circuit of a totem-pole NAND gate, which has got three stages.
·         Input Stage
·         Phase Splitter Stage
·         Output Stage
Input stage and Phase splitter stage have already been discussed. Output stage is called Totem-Pole because transistor Q3 sits upon Q4.
Q2 provides complementary voltages for the output transistors Q3 and Q4, which stack one above the other in such a way that while one of these conducts, the other is in cut-off.
Q4 is called pull-down transistor, as it pulls the output voltage down, when it saturates and the other is in cut-off (i.e. Q3 is in cut-off). Q3 is called pull-up transistor, as it pulls the output voltage up, when it saturates and the other is in cut-off (i.e. Q4 is in cut-off).
Diodes in input are protection diodes which conduct when there is large negative voltage at input, shorting it to the ground.
Tristate Output.
Normally when we have to implement shared bus systems inside an ASIC or externally to the chip, we have two options: either to use a MUX/DEMUX based system or to use a tri-state base bus system.
In the latter, when logic is not driving its output, it does not drive LOW neither HIGH, which means that logic output is floating. Well, one may ask, why not just use an open collector for shared bus systems? The problem is that open collectors are not so good for implementing wire-ANDs.
The circuit below is a tri-state NAND gate; when Enable En is HIGH, it works like any other NAND gate. But when Enable En is driven LOW, Q1 Conducts, and the diode connecting Q1 emitter and Q2 collector, conducts driving Q3 into cut-off. Since Q2 is not conducting, Q4 is also at cut-off. When both pull-up and pull-down transistors are not conducting, output Z is in high-impedance state.

Emitter coupled logic
Emitter coupled logic (ECL) is a non saturated logic, which means that transistors are prevented from going into deep saturation, thus eliminating storage delays. Preventing the transistors from going into saturation is accomplished by using logic levels whose values are so close to each other that a transistor is not driven into saturation when its input switches from low to high. In other words, the transistor is switched on, but not completely on. This logic family is faster than TTL.
Voltage level for high is -0.9 Volts and for low is -1.7V; thus biggest problem with ECL is a poor noise margin.
A typical ECL OR gate is shown below. When any input is HIGH (-0.9v), its connected transistor will conduct, and hence will make Q3 off, which in turn will make Q4 output HIGH.
When both inputs are LOW (-1.7v), their connected transistors will not conduct, making Q3 on, which in turn will make Q4 output LOW.
Metal Oxide Semiconductor Logic
MOS or Metal Oxide Semiconductor logic uses nmos and pmos to implement logic gates. One needs to know the operation of FET and MOS transistors to understand the operation of MOS logic circuits.
The basic NMOS inverter is shown below: when input is LOW, NMOS transistor does not conduct, and thus output is HIGH. But when input is HIGH, NMOS transistor conducts and thus output is LOW.

Normally it is difficult to fabricate resistors inside the chips, so the resistor is replaced with an NMOS gate as shown below. This new NMOS transistor acts as resistor.

Complementary Metal Oxide Semiconductor Logic
CMOS or Complementary Metal Oxide Semiconductor logic is built using both NMOS and PMOS. Below is the basic CMOS inverter circuit, which follows these rules:
·         NMOS conducts when its input is HIGH.
·         PMOS conducts when its input is LOW.
So when input is HIGH, NMOS conducts, and thus output is LOW; when input is LOW PMOS conducts and thus output is HIGH.

Field Programmable Gate Arrays(FPGA)
Field Programmable Gate Arrays are two dimensional arrays of logic blocks and flip-flops with a electrically programmable interconnections between logic blocks.
The interconnections consist of electrically programmable switches which is why FPGA differs from Custom ICs, as Custom IC is programmed using integrated circuit fabrication technology to form metal interconnections between logic blocks.
In an FPGA logic blocks are implemented using mutliple level low fanin gates, which gives it a more compact design compared to an implementation with two-level AND-OR logic. FPGA provides its user a way to configure:
1.     The intersection between the logic blocks and
2.     The function of each logic block.
Logic block of an FPGA can be configured in such a way that it can provide functionality as simple as that of transistor or as complex as that of a microprocessor. It can used to implement different combinations of combinational and sequential logic functions. Logic blocks of an FPGA can be implemented by any of the following:
1.     Transistor pairs
2.     combinational gates like basic NAND gates or XOR gates
3.     n-input Lookup tables
4.     Multiplexers
5.     Wide fan in And-OR structure.

Figure 1: Simplefied version of FPGA internal architecture.
Routing in FPGAs consists of wire segments of varying lengths which can be interconnected via electrically programmable switches. Density of logic block used in an FPGA depends on length and number of wire segments used for routing. Number of segments used for interconnection typically is a tradeoff between density of logic blocks used and amount of area used up for routing.
The ability to reconfigure functionality to be implemented on a chip gives a unique advantage to designer who designs his system on an FPGA It reduces the time to market and significantly reduces the cost of production.
Why do we need FPGAs ?
By the early 1980’s Large scale integrated circuits (LSI) formed the back bone of most of the logic circuits in major systems. Microprocessors, bus/IO controllers, system timers etc were implemented using integrated circuit fabrication technology. Random “glue logic” or interconnects were still required to help connect the large integrated circuits in order to :
1.     generate global control signals (for resets etc.)
2.     data signals from one subsystem to another sub system.
Systems typically consisted of few large scale integrated components and large number of SSI (small scale integrated circuit) and MSI (medium scale integrated circuit) components.
Intial attempt to solve this problem led to development of Custom ICs which were to replace the large amount of interconnect. This reduced system complexity and manufacturing cost, and improved performance.However, custom ICs have their own disadvantages. They are relatively very expensive to develop, and delay introduced for product to market (time to market) because of increased design time. There are two kinds of costs involved in development of Custom ICs:
1. cost of development and design
2. cost of manufacture
( A tradeoff usually exists between the two costs)

Therefore the custom IC approach was only viable for products with very high volume, and which were not time to market sensitive.
FPGAs were introduced as an alternative to custom ICs for implementing entire system on one chip and to provide flexibility of reporogramability to the user. Introduction of FPGAs resulted in improvement of density relative to discrete SSI/MSI components (within around 10x of custom ICs). Another advantage of FPGAs over CustomICs is that with the help of computer aided design (CAD) tools circuits could be implemented in a short amount of time (no physical layout process, no mask making, no IC manufacturing)

Figure 2: FPGA comparative analysis.

Logic Block

Logic Block

Logic block in an FPGA can be implemented in ways that differ in number of inputs and outputs, amount of area consumed, complexity of logic functions that it can implement, total number of transistors that it consumes. This section will describe some important implementations of logic blocks.


Crosspoint FPGA: consist of two types of logic blocks. One is transistor pair tiles in which transistor pairs run in parallel lines as shown in figure below:
transistor pair
second type of logic blocks are RAM logic which can be used to implement random access memory.
Plessey FPGA: basic building block here is 2-input NAND gate which is connected to each other to implement desired function.
Both Crosspoint and Plessey are fine grain logic blocks. Fine grain logic blocks have an advantage in high percentage usage of logic blocks but they require large number of wire segments and programmable switches which occupy lot of area.
Actel Logic Block: If inputs of a multiplexer are connected to a constant or to a signal, it can be used to implement different logic functions. for example a 2-input multiplexer with inputs a and b, select , will implement function ac + bc´. If b=0 then it will implement ac, and if a=0 it will implement bc´.
actel logic
Typically an Actel logic block consists of multiple number of multiplexers and logic gates.
Xilinx Logic block:
In Xilinx logic block Look up table is used to implement any number of different functionality. The input lines go into the input and enable of lookup table. The output of the lookup table gives the result of the logic function that it implements. Lookup table is implemented using SRAM. A k-input logic function is implemented using 2^k * 1 size SRAM. Number of different possible functions for k input LUT is 2^2^k. Advantage of such an architecture is that it supports implementation of so many logic functions, however the disadvantage is unusually large number of memory cells required to implement such a logic block in case number of inputs is large. Figure below shows 5-input LUT based implementation of logic block.Xilinx - LUT based
LUT based design provides for better logic block utilization. A k-input LUT based logic block can be implemented in number of different ways with tradeoff between performance and logic density.
logic block
An n-lut can be shown as a direct implementation of a function truth-table. Each of the latch holds the value of the function corresponding to one input combination. For Example: 2-lut shown in figure below implements 2 input AND and OR functions.

Altera Logic Block
Altera's logic block has evolved from earlier PLDs. It consists of wide fan in (up to 100 input) AND gates feeding into an OR gate with 3-8 inputs. If floating gate transistor based programmable switch is provide any vertical wire passing near AND gate can be used as input to the AND gate. IF each input signal is present both original and complemented form functional capability of block increases significantly. The advantage of large fan in AND gate based implementation is that few logic blocks can implement the entire functionality thereby reducing the amount of area required by interconnects. On the other hand disadvantage is the low density usage of logic blocks in a design that requires fewer input logic.
Another disadvantage is the use of pull up devices (AND gates) that consume static power. To improve power manufacturers provide low power consuming logic blocks at the expense of delay. Such logic blocks have gates with high Threshold as a result they consume less power. Such logic blocks can be used in non-critical paths.
Altera, Xilinx are coarse grain architecture.

Tradeoff - Size of Logic block Vs Performance

Size of logic block plays an important role in deciding density of logic blocks and area utilization in an FPGA. It also effects the performance of the FPGA.
  • A large size logic block implements more logic and hence requires less number of logic blocks to implement a functionality on the FPGA. On the other hand a large logic block will consume more space on the FPGA. So optimal size of logic block is one that optimally uses lesser number of logic blocks for functionality implementation while consuming as little space as possible.
  • Active logic area is generally less than total logic area due to presence of programmable connections. Total logic area is sum of active logic area and area consumed by programmable connections.
  • Routing area in an FPGA is typically more than the active area. It is 70 to 90 percent of total area in an FPGA.
  • In case of Lookup table based FPGA, a 4-input lookup table gives best results in terms of logic synthesised and area consumed.
  • Granularity of logic block has influence on performance of an FPGA. Typically higher granularity level results in lesser delay between input and output. As the granularity of logic block increases, number of levels of logic in critical path decreases, and hence delay in critical path decreases. On the flip side with increase in granularity level average fan out increases and number of switches also increases as each block has more pins. Also the length of wires increases with increase in size of logic block.

FPGA Routing Techniques

Routing architecture comprises of programmable switches and wires. Routing provides connection between I/O blocks and logic blocks, and between one logic block and another logic block.
The type of routing architecture decides area consumed by routing and density of logic blocks.
Routing technique used in an FPGA largely decides the amount of area used by wire segments and programmable switches as compared to area consumed by logic blocks.
A wire segment can be described as two end points of an interconnect with no programmable switch between them. A sequence of one or more wire segments in an FPGA can be termed as a track.
Typically an FPGA has logic blocks, interconnects and Input/Output blocks. Input Output blocks lie in the periphery of logic blocks and interconnect. Wire segments connect I/O blocks to wire segments through connection blocks. Connection blocks are connected to logic blocks, depending on the design requirement one logic block is connected to another and so on.
Xilinx Routing architecture
In Xilinx routing, connections are made from logic block into the channel through a connection block. As SRAM technology is used to implement Lookup Tables, connection sites are large. A logic block is surrounded by connection blocks on all four sides. They connect logic block pins to wire segments. Pass transistors are used to implement connection for output pins, while use of multiplexers for input pins saves the number of SRAM cells required per pin. The logic block pins connecting to connection blocks can then be connected to any number of wire segments through switching blocks.

there are four types of wire segments available :
  • general purpose segments, the ones that pass through switches in the switch block.
  • Direct interconnect : ones which connect logic block pins to four surrounding connecting blocks
  • long line : high fan out uniform delay connections
  • clock lines : clock signal provider which runs all over the chip.
Actel routing methodology
Actel's design has more wire segments in horizontal direction than in vertical direction. The input pins connect to all tracks of the channel that is on the same side as the pin. The output pins extend across two channels above the logic block and two channels below it. Output pin can be connected to all 4 channels that it crosses. The switch blocks are distributed throughout the horizontal channels. All vertical tracks can make a connection with every incidental horizontal track. This allows for the flexibility that a horizontal track can switch into a vertical track, thus allowing for horizontal and vertical routing of same wire. The drawback is more switches are required which add up to more capacitive load.
actel routing
Altera routing methodology
Altera routing architecture has two level hierarchy. At the first level of the hierarchy, 16 or 32 of the logic
blocks are grouped into a Logic Array Block, structure of the LAB is very similar to a traditional PLD. the connection is formed using EPROM- like floating-gate transistors. The channel here is set of wires that run vertically along the length of the FPGA. Tracks are used for four types of connections :

  • connections from output of all logic blocks in LAB.
  • connection from logic expanders.
  • connections from output of logic blocks in other LABs
  • connections to and from Input output pads
all four types of tracks connect to every logic block in the array block. The connection block makes sure that every such track can connect to every logic block pin. Any track can connect to into any input which makes this routing simple. The intra-LAB routing consists of segmented channel, where segments are as long as possible. Global interconnect structure called programmable interconnect array(PIA) is used to make connections among LABs. Its internal structure is similar to internal routing of a LAB. Advantage of this scheme is that regularity of physical design of silicon allows it to be packed tightly and efficiently. The disadvantage is the large number of switches required, which adds to capacitive load.
altera routing

FPGA Structural Classification

Programmble Logic Devices
There is a constant effort on the part of system designers to design systems with improved performance, efficiency and flexibility.
Today, if one wants to make effective and competitive use of these general purpose blocks, then one of the better ways is to use reconfigurable hardware that allows user programmability.
The first form of reconfigurable device was Programmable Logic Devices which consisted of arrays of AND and OR gates with programmable metal paths as interconnection between them. They could be programmed to into a single chip to meet specific requirements. PLDs later evolved into what was later known as FPGAs.
Basic structure of an FPGA includes logic elements, programmable interconnects and memory. Arrangement of these blocks is specific to particular manufacturer. On the basis of internal arrangement of blocks FPGAs can be divided into three classes:
Symmetrical arrays
This architecture consists of logic elements(called CLBs) arranged in rows and columns of a matrix and interconnect laid out between them. This symmetical matrix is surrounded by I/O blocks which connect it to outside world. Each CLB consists of n-input Lookup table and a pair of programmable flip flops. I/O blocks also control functions such as tri-state control, output transition speed. Interconnects provide routing path. Direct interconnects between adjacent logic elements have smaller delay compared to general purpose interconnet.
symmetrical arrays
Row based architecture
Row based architecture consists of alternating rows of logic modules and programmable interconnect tracks. Input output blocks are located in the periphery of the rows. One row may be connected to adjacent rows via vertical interconnect. Logic modules can be implemented in various combinations. Combinatorial modules contain only combinational elements which Sequential modules contain both combinational elements along with flip flops. This sequential modules can implement complex combinatorial-sequential functions. Routing tracks are divided into smaller segments connected by anti-fuse elements between them.
row based
Hierarchical PLDs
This architecture is designed in hierarchical manner with top level containing only logic blocks and interconnects. Each logic block contains number of logic modules. And each logic module has combinatorial as well as sequential functional elements. Each of these functional elements is controlled by the programmed memory. Communication between logic blocks is achieved by programmable interconnect arrays. Input output blocks surround this scheme of logic blocks and interconnects.
hierarchical design

Programming Methodology

Electrically programmable switches are used to program an FPGA. Performance of an FPGA in terms of area and logic density is a function of properties of these switches.
Properties of these programmable switches that make difference are on-resistance, parasitic capacitance, volatility, re-programmability, size etc.
Various approaches to provide user programmability are :

SRAM programming technology

Static RAM cells are used to control pass gates or multiplexers. To use pass gate as closed switch, boolean one is stored in SRAM cell. When zero is stored pass transistor provides high resistance between two wire segments. Figure a depicts this usage of SRAM.
To use SRAM as multiplexer, state of control values stored in SRAM decides which of the multiplexer inputs are connected to the output as shown in figure b.
Advantage of SRAM is that it provides fast re-programmability and integrated circuit fabrication technology is required to build it. While disadvantage is the space it consumes as minimum five transistors are required to implement a memory cell.

Floating Gate Programming

Technology found in ultaviolet erasable EPROM and electrically erasable EEPROM devices is used in FPGA from Altera. The programmable switch is a transistor that permanently be disabled.
Here again the advantage is reprogrammability but there is another advantage no external permanent memory source is need to program it at power-up. However it requires three additional processing steps over CMOS technology. Other disadvantages are high static power consumption due to pull up resistor and high ON-resistance of EPROM transistor.
floating gate
Electrically programmable EPROM is used by AMD and Lattice. Use of EEPROM gives advantage of easy reprogrammability. However EEPROM cell is twice as large as EPROM cell.

Antifuse programming methodology

An Antifuse is a two terminal device with an unprogrammed state providing very high resistance between its terminals. To create a low resistance link between the two terminals high voltage is applied accross the terminals to blow the antifuse. Extra bit of circuitry is required to program an antifuse. Antifuse technology is used by FPGA's from Actel, QuickLogic and Crosspoint.
Advantage of Antifuse is relatively small size and hence area reduction which is anulled by area consumed by extra circuitry to program it. Another big advantage is low series resistance and low parasitic capacitance.

FPGA Design Flow

One of the most important advantages of FPGA based design is that users can design it using CAD tools provided by design automation companies.
Generic design flow of an FPGA includes following steps:

System Design
At this stage designer has to decide what portion of his functionality has to be implemented on FPGA and how to integrate that functionality with rest of the system.
I/O integration with rest of the system
Input Output streams of the FPGA are integrated with rest of the Printed Circuit Board, which allows the design of the PCB early in design process. FPGA vendors provide extra automation software solutions for I/O design process.
Design Description
Designer describes design functionality either by using schema editors or by using one of the various Hardware Description Languages(HDLs) like Verilog or VHDL.
Once design has been defined CAD tools are used to implement the design on a given FPGA. Synthesis includes generic optimization, slack optimizations, power optimizations followed by placement and routing. Implementation includes Partition, Place and route. The output of design implementation phase is bit-stream file.
Design Verification
Bit stream file is fed to a simulator which simulates the design functionality and reports errors in desired behavior of the design. Timing tools are used to determine maximum clock frequency of the design. Now the design is loading onto the target FPGA device and testing is done in real environment.
Example :
Below given circuit consists of gates and flip flops. Combinational elements of the circuit are covered by a 4-input Look up table(4-LUT). Sequential elements in the input circuit map to flip flops on the FPGA. Placement of these elements is done in such a way as to minimize wiring during routing.

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