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UNIT II – SYNCHRONOUS
SEQUENTIAL CIRCUIT
Introduction
Combinational logic refers to circuits whose
output is strictly depended on the present value of the inputs. As soon as
inputs are changed, the information about the previous inputs is lost, that is,
combinational logics circuits have no memory. In many applications, information
regarding input values at a certain instant of time is required at some future
time. Although every digital system is likely to have combinational circuits,
most systems encountered in practice also include memory elements, which
require that the system be described in terms of sequential logic. Circuits
whose outputs depends not only on the present input value but also the past
input value are known as sequential logic circuits. The
mathematical model of a sequential circuit is usually referred to as a sequential
machine.
A general block diagram of a sequential circuit
is shown below in Figure 1.
Figure 1.
Block Diagram of Sequential Circuit.
The diagram consists of combinational circuit to
which memory elements are connected to form a feedback path. The memory
elements are devices capable of storing binary information within them. The
combinational part of the circuit receives two sets of input signals: one is primary
(coming from the circuit environment) and secondary (coming
from memory elements). The particular combination of secondary input variables
at a given time is called the present state of the circuit.
The secondary input variables are also know as the state variables.
The block diagram shows that the external outputs
in a sequential circuit are a function not only of external inputs but also of
the present state of the memory elements. The next state of the memory elements
is also a function of external inputs and the present state. Thus a sequential
circuit is specified by a time sequence of inputs, outputs, and internal
states.
Synchronous and Asynchronous Operation
Sequential circuits are divided into two main
types: synchronous and asynchronous. Their
classification depends on the timing of their signals.
Synchronous sequential circuits
change their states and output values at discrete instants of time, which are specified
by the rising and falling edge of a freerunning clock signal.
The clock signal is generally some form of square wave as shown in Figure 2
below.
Figure 2.
Clock Signal
From the diagram you can see that the clock
period is the time between successive transitions in the same
direction, that is, between two rising or two falling edges. State transitions
in synchronous sequential circuits are made to take place at times when the
clock is making a transition from 0 to 1 (rising edge) or from 1 to 0 (falling
edge). Between successive clock pulses there is no change in the information
stored in memory.
The reciprocal of the clock period is referred to
as the clock frequency. The clock width is
defined as the time during which the value of the clock signal is equal to 1.
The ratio of the clock width and clock period is referred to as the duty cycle.
A clock signal is said to be active high if the state changes
occur at the clock's rising edge or during the clock width. Otherwise, the
clock is said to be active low. Synchronous sequential
circuits are also known as clocked sequential circuits.
The memory elements used in synchronous
sequential circuits are usually flipflops. These circuits are binary cells
capable of storing one bit of information. A flipflop circuit has two outputs,
one for the normal value and one for the complement value of the bit stored in
it. Binary information can enter a flipflop in a variety of ways, a fact which
give rise to the different types of flipflops. For information on the
different types of basic flipflop circuits and their logical properties, see
the previous tutorial on flipflops.
In asynchronous
sequential circuits, the transition from one state to another is initiated by
the change in the primary inputs; there is no external synchronisation. The
memory commonly used in asynchronous sequential circuits are timedelayed
devices, usually implemented by feedback among logic gates. Thus, asynchronous
sequential circuits may be regarded as combinational circuits with feedback.
Because of the feedback among logic gates, asynchronous sequential circuits
may, at times, become unstable due to transient conditions. The instability
problem imposes many difficulties on the designer. Hence, they are not as
commonly used as synchronous systems.
Summary of the Types of Flipflop
Behaviour
Since memory elements in sequential circuits are
usually flipflops, it is worth summarising the behaviour of various flipflop
types before proceeding further.
All flipflops can be divided into four basic
types: SR, JK, D and T.
They differ in the number of inputs and in the response invoked by different
value of input signals. The four types of flipflops are defined in Table 1.
Table 1. Flipflop Types
FLIPFLOP NAME

FLIPFLOP SYMBOL

CHARACTERISTIC TABLE

CHARACTERISTIC EQUATION

EXCITATION TABLE


SR



Q(next) = S + R'Q
SR = 0



JK



Q(next) = JQ' + K'Q



D



Q(next) = D



T



Q(next) = TQ' + T'Q


Each of these flipflops can be uniquely
described by its graphical symbol, its characteristic table, its characteristic
equation or excitation table. All flipflops have output signals Q and Q'.
The characteristic table in the
third column of Table 1 defines the state of each flipflop as a function of
its inputs and previous state. Q refers to the present state
and Q(next) refers to the next state after the occurrence of
the clock pulse. The characteristic table for the RS flipflop shows that the
next state is equal to the present state when both inputs S and R are equal to
0. When R=1, the next clock pulse clears the flipflop. When S=1, the flipflop
output Q is set to 1. The equation mark (?) for the next state when S and R are
both equal to 1 designates an indeterminate next state.
The characteristic table for the JK flipflop is
the same as that of the RS when J and K are replaced by S and R respectively,
except for the indeterminate case. When both J and K are equal to 1, the next
state is equal to the complement of the present state, that is, Q(next) = Q'.
The next state of the D flipflop is completely
dependent on the input D and independent of the present state.
The next state for the T flipflop is the same as
the present state Q if T=0 and complemented if T=1.
The characteristic table is useful during the
analysis of sequential circuits when the value of flipflop inputs are known
and we want to find the value of the flipflop output Q after the rising edge of
the clock signal. As with any other truth table, we can use the map method to
derive the characteristic equation for each flipflop, which are shown in the
third column of Table 1.
During the design process we usually know the
transition from present state to the next state and wish to find the flipflop
input conditions that will cause the required transition. For this reason we
will need a table that lists the required inputs for a given change of state.
Such a list is called the excitation table, which is
shown in the fourth column of Table 1. There are four possible transitions from
present state to the next state. The required input conditions are derived from
the information available in the characteristic table. The symbol X in the
table represents a "don't care" condition, that is, it does not
matter whether the input is 1 or 0.
State Tables and State Diagrams
We have examined a general model for sequential
circuits. In this model the effect of all previous inputs on the outputs is
represented by a state of the circuit. Thus, the output of the circuit at any
time depends upon its current state and the input. These also determine the
next state of the circuit. The relationship that exists among the inputs,
outputs, present states and next states can be specified by either the state
table or the state diagram.
State Table
The state table representation of a sequential
circuit consists of three sections labelled present state, next
state and output. The present state designates the state of
flipflops before the occurrence of a clock pulse. The next state shows the
states of flipflops after the clock pulse, and the output section lists the
value of the output variables during the present state.
State Diagram
In addition to graphical symbols, tables or equations,
flipflops can also be represented graphically by a state diagram. In this
diagram, a state is represented by a circle, and the transition between states
is indicated by directed lines (or arcs) connecting the circles. An example of
a state diagram is shown in Figure 3 below.

Figure 3. State Diagram
The binary number inside each circle identifies
the state the circle represents. The directed lines are labelled with two
binary numbers separated by a slash (/). The input value that causes the state
transition is labelled first. The number after the slash symbol / gives the
value of the output. For example, the directed line from state 00 to 01 is labelled
1/0, meaning that, if the sequential circuit is in a present state and the
input is 1, then the next state is 01 and the output is 0. If it is in a
present state 00 and the input is 0, it will remain in that state. A directed
line connecting a circle with itself indicates that no change of state occurs.
The state diagram provides exactly the same information as the state table and
is obtained directly from the state table.
Example: This example is taken
from P. K. Lala, Practical Digital Logic Design and Testing, Prentice
Hall, 1996, p.155.
Consider a sequential circuit shown in Figure 4.
It has one input x, one output Z and two state variables Q1Q2 (thus having four
possible present states 00, 01, 10, 11).

Figure 4. A Sequential Circuit
The behaviour of the circuit is
determined by the following Boolean expressions:
Z = x*Q1

D1 =
x' + Q1

D2 =
x*Q2' + x'*Q1'

These equations can be used to form the state
table. Suppose the present state (i.e. Q1Q2) = 00 and input x = 0. Under these
conditions, we get Z = 0, D1 = 1, and D2 = 1. Thus the next state of the
circuit D1D2 = 11, and this will be the present state after the clock pulse has
been applied. The output of the circuit corresponding to the present state Q1Q2
= 00 and x = 1 is Z = 0. This data is entered into the state table as shown in
Table 2.


Output





Table 2. State table for the
sequential circuit in Figure 4.
The state diagram for the sequential circuit in
Figure 4 is shown in Figure 5.

Figure 5. State Diagram
of circuit in Figure 4.
State Diagrams of Various Flipflops
Table 3 shows the state diagrams of the four
types of flipflops.
NAME

STATE DIAGRAM

SR


JK


D


T


All four flipflops have the same number of
states and transitions. Each flipflop is in the set state when Q=1 and in the
reset state when Q=0. Also, each flipflop can move from one state to another,
or it can reenter the same state. The only difference between the four types
lies in the values of input signals that cause these transitions.
A state diagram is a very convenient way to
visualise the operation of a flipflop or even of large sequential components.
Analysis of Sequential Circuits
The behaviour of a sequential circuit is
determined from the inputs, the outputs and the states of its flipflops. Both
the output and the next state are a function of the inputs and the present
state.
The suggested analysis procedure of a sequential
circuit is set out in Figure 6 below.

Figure 6. Analysis procedure of sequential
circuits.
We start with the logic schematic from which we
can derive excitation equations for each flipflop input. Then, to obtain
nextstate equations, we insert the excitation equations into the
characteristic equations. The output equations can be derived from the
schematic, and once we have our output and nextstate equations, we can
generate the nextstate and output tables as well as state diagrams. When we
reach this stage, we use either the table or the state diagram to develop a
timing diagram which can be verified through simulation.
This example is taken from D. D. Gajski, Principles
of Digital Design, Prentice Hall, 1997, p.230.
Example 1.1.
Modulo4 counter
Derive the state table and state diagram for the
sequential circuit shown in Figure 7.

Figure 7. Logic schematic of a sequential
circuit.

SOLUTION:
STEP 1:
First we derive the Boolean expressions for the inputs of
each flipflops in the schematic, in terms of external input Cnt and the
flipflop outputs Q1 and Q0. Since there are two D flipflops in this example,
we derive two expressions for D1 and D0:
D0 = CntQ0 =
Cnt'*Q0 + Cnt*Q0'

D1 = Cnt'*Q1 + Cnt*Q1'*Q0 + Cnt*Q1*Q0'

These Boolean expressions are called excitation
equations since they represent the inputs to the flipflops of the
sequential circuit in the next clock cycle.
STEP 2:
Derive the nextstate equations by converting these
excitation equations into flipflop characteristic equations. In the case of D
flipflops, Q(next) = D. Therefore the next state equal the excitation
equations.
Q0(next) = D0 = Cnt'*Q0 + Cnt*Q0'

Q1(next) = D1 = Cnt'*Q1 + Cnt*Q1'*Q0 + Cnt*Q1*Q0'

STEP 3:
Now convert these nextstate equations into tabular form
called the nextstate table.





Each row is corresponding to a state of the
sequential circuit and each column represents one set of input values. Since we
have two flipflops, the number of possible states is four  that is, Q1Q0 can
be equal to 00, 01, 10, or 11. These are present states as shown in the table.
For the next state part of the table, each entry
defines the value of the sequential circuit in the next clock cycle after the
rising edge of the Clk. Since
this value depends on the present state and the value of the input signals, the
next state table will contain one column for each assignment of binary values
to the input signals. In this example, since there is only one input signal, Cnt,
the nextstate table shown has only two columns, corresponding to Cnt =
0 and Cnt = 1.
Note that each entry in the nextstate table
indicates the values of the flipflops in the next state if their value in the
present state is in the row header and the input values in the column header.
Each of these nextstate values has been computed
from the nextstate equations in STEP 2.
STEP 4:
The state diagram is generated directly from the nextstate
table, shown in Figure 8.

Figure 8.
State diagram
Each arc is labelled with the values of the input
signals that cause the transition from the present state (the source of the
arc) to the next state (the destination of the arc).
In general, the number of states in a nextstate
table or a state diagram will equal 2^{m }, where m is the number of
flipflops. Similarly, the number of arcs will equal 2^{m }x 2^{k}
, where k is the number of binary input signals. Therefore, in the state
diagram, there must be four states and eight transitions. Following these
transition arcs, we can see that as long as Cnt = 1, the sequential circuit
goes through the states in the following sequence: 0, 1, 2, 3, 0, 1, 2,....
On the other hand, when Cnt = 0, the circuit stays in its present state until
Cnt changes to 1, at which the counting continues.
Since this sequence is characteristic of modulo4
counting, we can conclude that the sequential circuit in Figure 7 is a modulo4
counter with one control signal, Cnt, which enables counting when Cnt = 1 and
disables it when Cnt = 0.
Below, we show a timing diagram, representing
four clock cycles, which enables us to observe the behaviour of the counter in
greater detail.

Figure 9. Timing Diagram

In this timing diagram we have assumed that Cnt
is asserted in clock cycle 0 at t_{0} and is disasserted in clock cycle
3 at time t_{4}. We have also assumed that the counter is in state Q1Q0
= 00 in the clock cycle 0. Note that on the clock's rising edge, at t_{1},
the counter will go to state Q1Q0 = 01 with a slight propagation delay; in
cycle 2, after t_{2}, to Q1Q0 = 10; and in cycle 3, after t_{3}
to Q1Q0 = 11. Since Cnt becomes 0 at t_{4}, we know that the counter
will stay in state Q1Q0 = 11 in the next clock cycle.
In Example 1.1 we demonstrated the analysis of a
sequential circuit that has no outputs by developing a nextstate table and
state diagram which describes only the states and the transitions from one
state to the next. In the next example we complicate our analysis by adding
output signals, which means that we have to upgrade the nextstate table and
the state diagram to identify the value of output signals in each state.
This example is taken from D. D. Gajski, Principles
of Digital Design, Prentice Hall, 1997, p.234.
Example 1.2
Derive the next state, the output table and the
state diagram for the sequential circuit shown in Figure 10.

Figure 10. Logic schematic of a sequential
circuit.
SOLUTION:
The input combinational logic in Figure 10 is the
same as in Example
1.1, so the excitation and the nextstate equations will be the same as in
Example 1.1.
Excitation equations:
D0 = CntQ0 =
Cnt'*Q0 + Cnt*Q0'

D0 = Cnt'*Q1 + Cnt*Q1'*Q0 + Cnt*Q1*Q0'

Nextstate equations:
Q0(next) = D0 = Cnt'*Q0 + Cnt*Q0'

Q1(next) = D0 = Cnt'*Q1 + Cnt*Q1'*Q0 + Cnt*Q1*Q0'

In addition, however, we have computed the output
equation.
Output equation: Y
= Q1Q0
As this equation shows, the output Y will equal
to 1 when the counter is in state Q1Q0 = 11, and it will stay 1 as long as the
counter stays in that state.
Nextstate and output table:


Output





State diagram:
Figure 11. State diagram of sequential
circuit in Figure 10.
Timing diagram:
Figure 12. Timing diagram of sequential circuit
in Figure 10.
Note that the counter will reach the state Q1Q0 =
11 only in the third clock cycle, so the output Y will equal 1 after Q0 changes
to 1. Since counting is disabled in the third clock cycle, the counter will
stay in the state Q1Q0 = 11 and Y will stay asserted in all succeeding clock
cycles until counting is enabled again.
Design of Sequential Circuits
The design of a synchronous sequential circuit
starts from a set of specifications and culminates in a logic diagram or a list
of Boolean functions from which a logic diagram can be obtained. In contrast to
a combinational logic, which is fully specified by a truth table, a sequential
circuit requires a state table for its specification. The first step in the
design of sequential circuits is to obtain a state table or an equivalence
representation, such as a state diagram.
A synchronous sequential circuit is made up of
flipflops and combinational gates. The design of the circuit consists of
choosing the flipflops and then finding the combinational structure which,
together with the flipflops, produces a circuit that fulfils the required
specifications. The number of flipflops is determined from the number of
states needed in the circuit.
The recommended steps for the design of
sequential circuits are set out below.
.State Reduction
Any design process must consider the problem of
minimising the cost of the final circuit. The two most obvious cost reductions
are reductions in the number of flipflops and the number of gates.
The number of states in a sequential circuit is
closely related to the complexity of the resulting circuit. It is therefore
desirable to know when two or more states are equivalent in all aspects. The
process of eliminating the equivalent or redundant states from a state
table/diagram is known as state reduction.
Example:
Let us consider the state table of a sequential circuit shown in Table 6.
Table 6. State table


Output





It can be seen from the table that the present
state A and F both have the same next states, B (when x=0) and C (when x=1).
They also produce the same output 1 (when x=0) and 0 (when x=1). Therefore
states A and F are equivalent. Thus one of the states, A or F can be removed
from the state table. For example, if we remove row F from the table and
replace all F's by A's in the columns, the state table is modified as shown in
Table 7.
Table 7. State F removed


Output





It is apparent that states B and E are
equivalent. Removing E and replacing E's by B's results in the reduce table
shown in Table 8.
Table 8. Reduced state table


Output





The removal of equivalent states has reduced the
number of states in the circuit from six to four. Two states are considered to
be equivalent if and only if for every input sequence the
circuit produces the same output sequence irrespective of which one of the two
states is the starting state.
Design of Sequential Circuits
This example is taken from M. M. Mano, Digital
Design, Prentice Hall, 1984, p.235.
Example 1.3
We wish to design a synchronous
sequential circuit whose state diagram is shown in Figure 13. The type of
flipflop to be use is JK.

Figure 13. State diagram
From the state diagram, we can
generate the state table shown in Table 9. Note that there is no output section
for this circuit. Two flipflops are needed to represent the four states and are
designated Q0Q1. The input variable is labelled x.
Table 9. State table.





We shall now derive the excitation table and the
combinational structure. The table is now arranged in a different form shown in
Table 11, where the present state and input variables are arranged in the form
of a truth table. Remember, the excitable for the JK flipflop was derive in
Table 10.
Excitation table for JK flipflop
Output Transitions

Flipflop inputs




Table
11. Excitation table of the circuit


Input

Flipflop Inputs






In the first row of Table 11, we have a
transition for flipflop Q0 from 0 in the present state to 0 in the next state.
In Table 10 we find that a transition of states from 0 to 0 requires that input
J = 0 and input K = X. So 0 and X are copied in the first row under J0 and K0
respectively. Since the first row also shows a transition for the flipflop Q1
from 0 in the present state to 0 in the next state, 0 and X are copied in the
first row under J1 and K1. This process is continued for each row of the table
and for each flipflop, with the input conditions as specified in Table 10.
The simplified Boolean functions for the
combinational circuit can now be derived. The input variables are Q0, Q1, and
x; the output are the variables J0, K0, J1 and K1. The information from the
truth table is plotted on the Karnaugh maps shown in Figure 14.
Figure 14. Karnaugh Maps
The flipflop input functions are derived:
J0
= Q1*x' K0 = Q1*x

J1
= x
K1 = Q0'*x' + Q0*x = Q0x

Note: the symbol is exclusiveNOR.
The logic diagram is drawn in Figure 15.

Figure 15. Logic diagram of the sequential
circuit.
Design of Sequential Circuits
This example is taken
from P. K. Lala, Practical Digital Logic Design and Testing, Prentice
Hall, 1996, p.176.
Example 1.4
Design a sequential circuit whose state tables are specified in Table 12, using
D flipflops.
Table 12.
State table of a sequential circuit.


Output





Table 13.
Excitation table for a D flipflop.
Output Transitions

Flipflop inputs




Next step is to derive the excitation table for
the design circuit, which is shown in Table 14. The output of the circuit is
labelled Z.
Table 14.
Excitation table


Input

Flipflop Inputs

Output







Now plot the flipflop inputs and output
functions on the Karnaugh map to derive the Boolean expressions, which is shown
in Figure 16.
Figure 16. Karnaugh maps
The simplified Boolean expressions are:
D0 = Q0*Q1' + Q0'*Q1*x

D1 = Q0'*Q1'*x + Q0*Q1*x + Q0*Q1'*x'

Z = Q0*Q1*x

Finally, draw the logic diagram.
Figure 17. Logic diagram of the sequential
circuit.
Design of Counters
A sequential circuit that goes through a
prescribed sequence of states upon the application of input pulses is called a counter.
The input pulses, called count pulses, may be clock pulses. In
a counter, the sequence of states may follow a binary count or any other
sequence of states. Counters are found in almost all equipment containing
digital logic. They are used for counting the number of occurrences of an even
and are useful for generating timing sequences to control operations in a
digital system.
Of the various sequences a counter may follow,
the straight binary sequence is the simplest and most straight forward. A
counter that follows the binary sequence is called a binary counter. An nbit
binary counter consists of n flipflops and can count in binary from 0 to 2^{n}
 1.
Design of Counters
This example is taken from T. L. Floyd, Digital
Fundamentals, Fourth Edition, Macmillan Publishing, 1990, p.395.
Example 1.5
A counter is first described by a state diagram, which is shows the sequence of
states through which the counter advances when it is clocked. Figure 18 shows a
state diagram of a 3bit binary counter.

Figure 18. State diagram of a 3bit binary counter.
The circuit has no inputs
other than the clock pulse and no outputs other than its internal state
(outputs are taken off each flipflop in the counter). The next state of the
counter depends entirely on its present state, and the state transition occurs
every time the clock pulse occurs. Figure 19 shows the sequences of count after
each clock pulse.
Fig.19 Count sequence after each pulse
Once the sequential circuit is defined by the
state diagram, the next step is to obtain the nextstate table, which is
derived from the state diagram in Figure 18 and is shown in Table 15.
Table 15.
State table





Since there are eight states, the number of
flipflops required would be three. Now we want to implement the counter design
using JK flipflops.
Next step is to develop an excitation table from
the state table, which is shown in Table 16.
Table 16.
Excitation table

Flipflop inputs








Now transfer the JK states of the flipflop
inputs from the excitation table to Karnaugh maps to derive a simplified
Boolean expression for each flipflop input. This is shown in Figure 20.

Figure 20. Karnaugh maps
The 1s in the Karnaugh maps of Figure 20 are
grouped with "don't cares" and the following expressions for the J
and K inputs of each flipflop are obtained:
J0 = K0 = 1

J1 = K1 = Q0

J2 =

The final step is to implement the combinational
logic from the equations and connect the flipflops to form the sequential
circuit. The complete logic of a 3bit binary counter is shown in Figure 21.

Figure 21. Logic diagram
of a 3bit binary counter
Design of Counters
This example is taken from M. M. Mano, Digital
Design, Prentice Hall, 1984, p.243.
Example 1.6
Design a counter specified by the state diagram in Example
1.5 using T flipflops. The state diagram is shown here again in Figure 22.

Figure 22. State diagram of a 3bit binary counter.
The state table will be the same as in Example
1.5.
Now derive the excitation table from the state
table, which is shown in Table 17.
Table 17.
Excitation table.

Flipflop inputs








Next step is to transfer the flipflop input functions
to Karnaugh maps to derive a simplified Boolean expressions, which is shown in
Figure 23.

Figure 23. Karnaugh maps
The following expressions are obtained:
T0 =
1; T1 = Q0;
T2 = Q1*Q0
Finally, draw the logic diagram of the circuit
from the expressions obtained. The complete logic diagram of the counter is
shown in Figure 24.

Figure 24. Logic diagram of 3bit binary counter.
Now that you have reached the end of the
tutorial, you should be able to understand the basic concept of sequential
circuits. You should be able to analyse and design a basic sequential circuit.
Now you can practice some of the exercises using the analysis and design
procedures shown in the examples.
Exercises
You can try some of these exercises which covers
the analysis and design of sequential circuits.
Analysis of Sequential Circuits.
1. Derive a)
excitation equations, b) next state equations, c) a state/output table, and d)
a state diagram for the circuit shown in Figure 1.1. Draw the timing diagram of
the circuit.

Figure 1.1
2. Derive a)
excitation equations, b) next state equations, c) a state/output table, and d)
a state diagram for the circuit shown in Figure 1.2.

Figure 1.2
3. Derive a)
excitation equations, b) next state equations, c) a state/output table, and d)
a state diagram for the circuit shown in Figure 1.3.

Figure 1.3
4. Derive the
state output and state diagran for the sequential circuit shown in Figure 1.4.

Figure 1.4
5. A
sequential circuit uses two D flipflops as memory elements. The behaviour of
the circuit is described by the following equations:
D1 = Q1 + x'*Q2

D2 = x*Q1' + x'*Q2

Z = x'*Q1*Q2 + x*Q1'*Q2'

Derive the state table and draw the state diagram
of the circuit.
Design of Sequential Circuits.
6. Design a
sequential circuit specified by Table 6.1, using JK flipflops.
Table 6.1


Output





7. Design the
sequential circuit in question 6, using T flipflops.
8. Design a
mod5 counter which has the following binary sequence: 0, 1, 2, 3, 4. Use JK
flipflops.
9. Design a
counter that has the following repeated binary sequence: 0, 1, 2, 3, 4, 5, 6,
7. Use RS flipflops.
10. Design a counter with
the following binary sequence: 1, 2, 5, 7 and repeat. Use JK flipflops.
11. Design a counter with
the following repeated binary sequence: 0, 4, 2, 1, 6. Use T flipflops.
12. Design a counter that
counts in the sequence 0, 1, 3, 6, 10, 15, using four a) D, b) SR, c) JK and d)
T flipflops.